Technical Field
The present invention, generally, relates to vertical electrical connections for 3D (three-dimensional) integration technology, more particularly, to via structures for electric connection and methods for fabricating thereof.
Related Art
In conventional through via structures such as TSV (Through Silicon Via) and TGV (Through Glass Via), both ends of the through via are typically surrounded by rigid materials such as Si, Metal or BEOL (Back End Of Line, SiO2), which may have a higher Young's modulus. Since the through via typically has a larger CTE (Coefficient of Thermal Expansion) than the substrate, mismatch between the though via and the substrate in the CTE may cause stress around the ends of the through via when a change in temperature occurs during a fabrication process, resulting in failure of electrical connections.
Recently, solder vias have been attracting attention since such via structures can be fabricated by IMS (Injection Molded Solder) technology, which provides low cost solutions for 3D integration. However, it is noted that solder has larger CTE (21.7 ppm for SAC (SnAgCu)) than that of Copper (16.2 ppm), which is still higher than typical substrate materials (2.6 ppm for silicon, ˜3 ppm for glass). In the TGV, the solder via would pump up a rigid metal layer that covers the solder via, which results in cracks in the brittle glass substrate around the ends of the solder via.
In relation to the stress generated around the via structure, recently, low stress bond pad design has been proposed for solder interconnection on TSVs (X. Zhang et al., “Low-Stress Bond Pad Design for Low Temperature Solder Interconnections on Through-Silicon Vias (TSVs)”, IEEE Transactions on Component, Packaging and Manufacturing Technology 1(4): 510-518. 2011). However, the proposed bound pad design is limited for solder interconnection formed on a pad located above TSVs, therefore, there still remains a need for improved via structures that are capable of reducing stress generated around the end of the via due to the mismatch between the via and the substrate in the CTE.